The quest for smaller and smaller memory cells to allow more and more memory capacity in integrated circuit memories is a well known goal. The search for methods of fabricating higher density memories has led some to place an entire memory cell including transistor and a storage capacitor in a single deep cavity (trench) formed on the surface of integrated circuit substrate. See, for example, U.S. Pat. Application Ser. No. 679,663, which is assigned to the assignee of the present application, and is hereby incorporated by reference. The inclusion of both the transistor and the capacitor in a single trench has led to parasitic capacitance problems. Specifically the bit line and word line capacitive coupling to the memory cell is great enough to disrupt the data stored in the memory cell. In addition, the transistor structure in the above mentioned application provides a toroidal shaped source drain and channel region. This increased area in the structure of the transistor creates leakage problems from both the bit line and the storage node. Several memory cell designs have used polysilicon transistors which are enclosed within the trench. However, the channel leakage characteristics of polycrystalline silicon transistors are inferior to those of transistors formed in bulk silicon. For an example of a memory cell using a polycrystalline transistor see published European Pat. Application Ser. No. 108,390, which is hereby incorporated by reference.